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Digital I/O Signaling and Connections


An output signal can be generated on any available output capable GPIO pin of the given IPC being used. Output signals are single pulses of a configurable pulse width.

There is a hard-coded 10ms setup time generated for every signal, so if multiple output signals happen to be back-to-back there is guaranteed to be at least 10ms of low signal state before the rising edge.

Timing diagram for output signals


Input signals used to start assemblies should look similar to the following timing diagram. Supercoach is looking for a rising edge.

Timing diagram for input signals

The input signal should be held high after the rising edge for at least 10ms. In the diagram above it is held high from 20ms to 120ms, or 100ms total, just as an illustration.

Hardware Specific Settings

Siemens IPC520a

The following schematic shows the general biasing required for the GPIO signals to function correctly.

The important points shown in the schematic below are

  • DQ_L must be tied to +24V
  • DQ_N and DI_M must be tied to GND
  • All DQ outputs must be pulled down to GND via 10K Ω 1-Watt resistors
  • All DI inputs must be pulled up to +24V via 1K Ω 1-Watt resistors
Schematic view of how the connector must be wired.

The following tables are taken directly from the instruction manual for the IPC520a and describe the voltages levels required to signify logical high/low signals.

IPC520a digital output specifications from Siemens operating instruction manual